1. Field of the Invention
The present invention relates to a SSC chip, a fiber array attached with the SSC chip, a PLC module attached with the SSC chip and a method for manufacturing the SSC chip.
2. Description of the Related Art
An increase of Δ (relative index difference) of a waveguide is been studied lately in order to integrate and miniaturize a planar lightwave circuit (PLC). However, a large coupling loss is generated in coupling a PLC chip having the planar lightwave circuit of the high Δ waveguide with a fiber array in which normal single mode fibers (SMF) are arrayed because a mode field of the high Δ waveguide is different from that of the single mode fiber. Still more, a large coupling loss is generated in coupling PLCs whose Δ of the waveguide is different because the mode field of the high A waveguide is different from the low Δ waveguide. Then, in order to reduce the mismatching of the mode fields, various spot-size converters (SSC) are being studied.
For example, as prior arts relating to the spot-size converter (SSC), there are technologies described in non-patent documents [1] Kei Watanabe et. al., Conference of Electronic Society of the Institute of Electronics, Information and Communication Engineers, C-3-7, PLC chip130 (2007), [2] Kei Watanabe, General Assembly of the Institute, c-3-81, PLC chip 251 (2005), [3] Mikitaka Ito et. al., Conference of Electronic Society of the Institute, c-3-13, PLC chip 146 (2003), [4] Mikitaka Ito et. al., General Assembly of the Institute, c-3-72, PLC chip 212 (2003) and [5] Takayuki Mizuno et. al., General Assembly of the Institute, c-3-73, PLC chip 213 (2003). Watanabe [1] describes a double-core type SSC in which a high Δ core having a tapered structure is disposed in a center of a low Δ core. Watanabe [2] describes a laminate SSC in which the high Δ core having the tapered structure is laminated on the low A core. Ito [3] describes a vertically and horizontally tapered SSC in which a core diameter is extended in vertical and horizontal directions. Ito [4] describes a SSC in which the core is formed into a shape of T by shortening an etching time of the vertically and horizontally tapered SSC. Mizuno [5] describes a narrowly tapered SSC in which a core diameter reduces in the horizontal direction.
Still more, as prior art technologies for creating a tapered core extending in the vertical direction, there are technologies described in Japanese Patent Application Laid-open Nos. Hei.09-197153, Hei. 07-027934 and 2002-156539. The JP Hei.09-197153 describes a technology of creating steps on a substrate or a cladding layer by means of etching and of creating a core extending in the vertical direction by that step. JP Hei. 07-027934 describes a technology of creating a tapered core by differentiating resists and core etching rates in photolithography. JP 2002-156539 describes a technology of creating a tapered core by creating steps on the core and by averaging the steps by depositing a core thin film on the steps.
By the way, the prior arts described above fabricate the PLC chip having the planar lightwave circuit so as to add the SSC at an end of the light waveguide to connect the light waveguide and fibers whose spot sizes are different at low loss. Due to that, this arrangement has had a problem that it adds a yield of the SSC to a yield of the light waveguide of the PLC chip itself, thus lowering a yield of the whole.
Still more, if the vertical and horizontal tapered core whose core diameter is enlarged in the vertical and horizontal directions is to be created in the PLC chip itself, a process of enlarging the core diameter in the vertical direction is required beside the process of enlarging the core in the horizontal direction by a photo-mask, so that there has been a problem that a manufacturing cost of the PLC chip itself increases by the increase of the processing steps.